02 Oct
RANDSTAD INDIA
Hyderabad
Role Overview
We are seeking a highly motivated Senior Staff ASIC Digital Design Engineer to join our Hyderabad Design Center. In this role, you will lead RTL synthesis, timing, and low-power implementation for cutting-edge MCU SoCs. You’ll collaborate closely with cross-functional teams, drive design methodology improvements, and mentor junior engineers, playing a key role in delivering high-quality, next-generation silicon.
Key Responsibilities
- Own and drive RTL synthesis & constraints generation/validation for MCU SoCs.
- Ensure designs meet performance, power, and area (PPA) specifications.
- Act as a bridge between frontend and backend teams, resolving timing and hand-off issues.
- Support formality checks and low-power implementation flows.
- Develop & implement current design/implementation methodologies to improve productivity and quality.
- Lead design reviews and mentor junior engineers.
- Collaborate with cross-functional teams to resolve collateral issues and optimize PPA.
Required Qualifications
- Bachelor’s degree in Electronics/Electrical/Computer Engineering (or similar).
- 12+ years of IC design experience (or 9+ years with MSEE/PhD).
- Proven track record of delivering high-quality designs.
- Expertise with EDA tools for synthesis, static timing analysis, and constraints validation.
- Strong understanding of digital design principles, timing analysis, and verification methodologies.
- Scripting experience (Shell, Perl, Python, TCL) a plus.
- Strong communication & mentoring skills.
Preferred Qualifications
- Experience with low-power design methodologies.
- Exposure to SoC design and integration.
- Understanding of DFT flows.
- Experience with Automotive SoC designs.
📌 Lead ASIC Design Engineer
🏢 RANDSTAD INDIA
📍 Hyderabad
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