02 Oct
Mulya Technologies
Hyderabad
DV lead/manager
www.Sevyamultimedia.Com
Hyderabad
About Us
We are a technology consulting company delivering best-in class Chip Design Services.
Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.
Chip Design Services
Analog IP Design
Foundation - OpAmp, Bandgap
IOs - GPIO, I2C, LVDS
Clocking - PLL
Power - LDO
SoC Design
RTL Design, Integration, Lint/CDC/RDC, UPF
IP/SoC UVM Verification
PPA, Synthesis, Constraints Management
Physical Design, Timing Closure, ECOs
Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC
DV lead/manager to verify IP/SoC using System Verilog/UVM
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Exposure to various interface IP like I2C/SPI/UART/USB/NVM/PCIe;
Buses AXI/AHB/APB;
ARM based SoC designs is needed.
Skills:
- Overall 7-15+ years industry experience with 5+ years in Design Verification using System-Verilog/C/UVM.
- Generic knowhow on Digital Design and Verification methodologies.
- Experience in System Verilog/UVM based IP/SoC verification using advanced technologies.
- Good understanding of Constraint based Random verification;
VIP coding;
Test Plan design;
Test cases coding;
Coverage strategies and measurement
- Proficient in EDA tools used for Design Verification (e.G. Cadence/Mentor/Synopsys simulation suites;
Verilator).
- Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
- Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills
Traits:
- Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a solid sense of urgency.
- Solutions orientation;
Quality driven;
Execution minded
Contact: Uday Bhaskar
Mulya Technologies
"Mining the Knowledge Community"
Email id : [email protected]
📌 Verification Engineering Manager
🏢 Mulya Technologies
📍 Hyderabad
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