Cadence Design Systems, Inc.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Experience and Education requirements : MTech/BTech
Design and lead high speed IP (USB3, PCIE, DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development – analog design, layout, digital design, documentation and silicon validation. Would be required to participate in customer facing discussions.
- Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc.
- Must have participated in full cycles of analog IP creation – right from spec to silicon debug and char
- Should have 8+ years of experience
- Must have good communication skills and should be team player.
- Working experience in PHY (PCIE, USB2, USB3) development is desired
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