Q-335 Lead Design Engineer

Q-335 Lead Design Engineer

14 Sep
|
Cadence Design Systems, Inc.
|
Bangalore Rural

14 Sep

Cadence Design Systems, Inc.

Bangalore Rural

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.



- Job Description:  



- Responsibilities includes knowledge of Serdes IP design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.

- Defining DFT architecture - # of Scan chains, clock domains and DFT wrapper for analog-digital boundaries, clock / reset bypassing etc..For both Testchip and IP versions.

- Interact with PD team for Scan insertion and generating patterns to determine the Test and Fault coverage against the target goals as per Specifications

- DC/AC and At-speed Scan, MBIST, JTAG and test logics at IP and Test chip level etc..



- interfaces with PD team to analyze coverage for Pre- Scan and post-scan stitched netlist, analyze timing paths for Scan hold fixes and subsequent test vector generation for functional and scan.



We’re doing work that matters. Help us solve what others can’t.

The original job offer can be found in Kit Job:
https://www.kitjob.in/job/18952363/q-335-lead-design-engineer-bangalore-rural/?utm_source=html

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