Cadence Design Systems, Inc.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Job Description:
- Responsibilities includes knowledge of Serdes IP design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.
- Defining DFT architecture - # of Scan chains, clock domains and DFT wrapper for analog-digital boundaries, clock / reset bypassing etc..For both Testchip and IP versions.
- Interact with PD team for Scan insertion and generating patterns to determine the Test and Fault coverage against the target goals as per Specifications
- DC/AC and At-speed Scan, MBIST, JTAG and test logics at IP and Test chip level etc..
- interfaces with PD team to analyze coverage for Pre- Scan and post-scan stitched netlist, analyze timing paths for Scan hold fixes and subsequent test vector generation for functional and scan.
We’re doing work that matters. Help us solve what others can’t.
Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.
Company Description At Palo Alto Networks® everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. We have the vision o [...]
- 4+ years of professional software development experience - 3+ years of programming experience with at least one modern language such as Java, C++, or C# including object-oriented design - 2+ yea [...]
Job Description Hybris eCommerce developers with min. 3 years of experience in developing core applications, APIs and REST Services on Hybris 6.x platform. Good to have exposure in Financial Se [...]
Hiring for Java Developer - Bengaluru / Hyderabad Center, TEKsystems Global Services , Role and Responsibilities Identify application functionality within compliance specifications to create scalab [...]