Cadence Design Systems, Inc.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
• Programming in C/C++
• Design, development Bare Metal drivers
• Development and upstream of Linux kernel drivers
• Bring-up of drivers on Virtual, Simulation, and FPGA platforms
• Test automation and compliance testing
• Experience in high performance SOC architecture (ARM integration) with focus on system-level trade-offs
• Development of functional and behavioral (cycle-level) models in C++/SystemC
• Experience running RTL/UVM System Verilog simulation environments for model validation
• Experience in creating workloads for different SoC components at required levels of abstraction
• Knowledge of scripting languages (bash, python, perl)
• Excellent communication skills and ability to work in a team spread over multiple time-zones
• BS/MS degree in Computer Science or Electrical Engineering, or equivalent practical experience
• Design and develop bare-metal and Linux drivers and/or cycle approximate C++/System C models for Cadence's IPs like DDR controller, PCIe controller, etc for use in architectural exploration and performance analysis at different levels - subsystem and SoC level.
• Design and develop protocol specific functional models for various Cadence's interface IPs like USB, Ethernet, UFS, DP, etc
• Interact with IP designers and architects to understand various IP design/implementation specification and behavior
• Participate in defining traffic patterns, tools and methodology based on the model to help identify functional issues and performance bottlenecks
• Documentation of design specifications, user guides, implementation details, FAQ's, application notes, etc
• Responding to customer cases and reproducing performance issues reported by the customer
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