Part-Time Design Verification Engineer (SoC/System-Level) (Malappuram)

Part-Time Design Verification Engineer (SoC/System-Level) (Malappuram)

Seeking an experienced Design Verification Engineer to work on SoC and system-level verification activities. The role includes developing testbenches, integrating VIP, performing system-level validation, and debugging complex issues.

Key Responsibilities

- Perform SoC/system-level verification using SystemVerilog and UVM.
- Develop and maintain testbench architecture and verification infrastructure.
- Integrate VIP and support C-based verification flows.
- Conduct functional, regression, and system-level validation.
- Debug issues across RTL, firmware, and system components.

Required Skills

- Robust expertise in SystemVerilog / UVM.
- Proficiency in Python, Perl, or Shell scripting.
- Experience with C-based verification.
- Strong debugging skills and understanding of complex SoC environments.

Preferred Skills

- Knowledge of PCIe, HBM, Ethernet, or D2D technologies (added advantage).

📌 Part-Time Design Verification Engineer (SoC/System-Level) (Malappuram)
🏢 Abidott Solutions (OPC) Private
📍 Malappuram