Lead Verification Engineer (JYY160)

Lead Verification Engineer (JYY160)

17 Mar
NXP Semiconductors

17 Mar

NXP Semiconductors


NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.

Job Summary

The Verification role will involve many aspects of Functional, Performance verification using most effective methodologies in context of Module/Subsystem/SoC /System Level.

A strong ability to map requirements into a traceable verification plan is important. The ideal candidate will partner with local and global SoC and IP developers to drive best practices with a target of ongoing productivity improvement. A “zero-defect” mindset is a key enabler. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, formal verification and emulation, debugging failures and creating simulation cases for various studies

Expectations include:

- Verification planning;

- Verification test bench development and implementation;

- Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs;

- Development of direct and constrained-random stimulus;

- Understands and analyzes RTL code, functional, assertion coverage results;

- Understands Develop functional coverage;

- Understands and develops system Verilog assertions;

- Understands and implements formal verification methods;

- Strong skills in debug, failure re-creation and root cause analysis

- Applicant should have efficient debugging and logic skills.

Job Qualifications

BTech/MTech with 5-8 years’ experience in SOC/IP/Subsystem verification of multimillion Gate complex Design with multiple clocks/power domains. Experience in below areas with strong hands on knowledge in below areas is needed

- C and UVM/SV based Test environment,

- HDLs (Verilog/VHDL), simulators (Synopsys/Cadence/Mentor) is a MUST

- Understanding of the design/architecture and ability to debug RTL/Gate netlist is MUST

- Coverage driven Verification for addressing Functional, Performance requirement of the SoC, regression management

- Microcontroller architecture, ARM Cores, Interconnect(NIC, FlexNoC), Cache Coherency,

- Bus Protocols like AHB/AMBA,AXI, ACE

- memory controllers (Flash, SRAM,DDR3/4/LPDDR) 

- Networking protocols like PCIe, MIPI, GPU (Graphics processing), VPU (Video Processing), Ethernet, USB, Image, automotive protocols like LIN, CAN, FlexRay would be an advantage

- Formal verification methodologies and Apps, AVIP, PinMuxing Verification, Randomization

- Test pattern debugging and testing for verification and automatic testers

- Low Power intent verification using CPF, UPF

- Automation of verification collateral using scripts in Perl, Python

- Exposure to pre silicon validation/emulation (Palladium, Zebu)/FPGA Prototyping would be a plus

- Power management understanding

The original job offer can be found in Kit Job:

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