ALP Consulting Limited
RTL Design - SMTS/LEAD MTS/Principal engineer
Experience7 TO 19YRS
Skills/ Keywords MandatoryRTL Design, Verilog, System verilog, UVM, AXI3/4
RTL Design Engineer for DDR Memory Controller IP development team.
Position is based in Bangalore.
The role would include design and support of the RTL of the DDR Memory Controller solution. All leading DDR memory protocols will be supported including DDR4/LPDDR4.
The work involved will be working with the existing RTL, addition of new features into the RTL,
ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines
Education B.E/B-Tech/ME/MTech in electronics/electrical/VLSI
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