Senior ASIC RTL Design engineer For Bangalore/Chennai/ Hyderabad/Noida [K-809]

Senior ASIC RTL Design engineer For Bangalore/Chennai/ Hyderabad/Noida [K-809]

13 Nov
|
SMARTSOC SOLUTIONS PRIVATE LIMITED
|
Chennai district

13 Nov

SMARTSOC SOLUTIONS PRIVATE LIMITED

Chennai district

Skill set required:





- RTL Design Engineer for DDR Memory Controller IP development team.

- The role would include design and support of the RTL of the DDR Memory Controller solution . All leading DDR memory protocols will be supported including DDR4/LPDDR4.

- The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

- Position Requirements:

- RTL Design using Verilog is a must.

- System Verilog experience and experience with UVM based environment usage / debugging is required.

- AXI3/4 experience is a desired.



- DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.

- Prior experience in IP development teams would be an added advantage.



Academic Qualification:



- BE/B.Tech in ECE /M.Tech in VLSI





If interested, Please share updated CV to [email protected] or refer who would like to explore this opportunity

The original job offer can be found in Kit Job:
https://www.kitjob.in/job/25375204/senior-asic-rtl-design-engineer-for-bangalore-chennai-hyderabad-noida-k-809-chennai-district/?utm_source=html

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