Job Summary
We are seeking a skilled Design Verification (DV) Engineer with strong experience in DDR/LPDDR memory subsystem verification. The candidate will be responsible for verifying high-speed memory controller designs to ensure functional correctness, performance, and protocol compliance.
Key Responsibilities
Develop and execute verification plans for DDR/LPDDR memory controllers and PHY interfaces
Create SystemVerilog/UVM-based testbenches and verification environments
Write test cases, sequences, and checkers for protocol validation
Perform functional, code, and assertion coverage analysis and closure
Debug RTL issues and collaborate with design teams to resolve bugs
Work on protocol compliance for DDR4/DDR5/LPDDR4/LPDDR5
Integrate VIPs (Verification IP) for DDR/LPDDR protocols
Analyze waveform/debug failures using tools like Verdi, DVE, or SimVision
Contribute to regression runs and automation frameworks
Ensure quality and timely delivery of verification milestones
Required Skills
Solid knowledge of SystemVerilog and UVM methodology
Experience in DDR/LPDDR protocols (DDR3/DDR4/DDR5, LPDDR4/LPDDR5)
Understanding of memory controller architecture and PHY interfaces
Experience with industry-standard simulators (VCS, Xcelium, Questa)
Debugging skills with waveform tools
Knowledge of assertions (SVA) and coverage-driven verification
Familiarity with scripting languages like Python, Perl, or Shell
Preferred Qualifications
Experience with verification IPs (Synopsys/Cadence/Mentor DDR VIP)
Knowledge of low-power verification concepts
Experience in performance verification and stress testing
Exposure to emulation platforms or FPGA prototyping is a plus
Understanding of JEDEC standards
Education
Bachelor’s or Master’s degree in Electronics/Electrical/Computer Engineering