DFT Engineer (Staff/Sr. Staff)

About the Role
Responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug and diagnostics needs of the memories in design.

Responsibilities
Work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design, and backend implementation flow.
The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight.
Involve in high quality pattern release to test team and support silicon bring-up and yield improvement.

Qualifications
ASIC Design DFT professional with 10 to 18 years of related work experience with a broad mix of technologies including:

Required Skills




Knowledge of the latest state of the art trends in Memory testing and silicon engineering
Hands on experience in JTAG & IJTAG protocols, MBIST and scan architectures .
Verification skills including System Verilog, LEC and validating test timing of the design
Experience working with gate-level simulations, and debug with VCS and other simulators
Understanding the testbench in System Verilog, UVM/VMM is an addon
Post-silicon validation and debug experience, ability to work with ATE patterns
Strong verbal communication skills and ability to thrive in a dynamic setting
Scripting skills: Python/Perl

📌 DFT Engineer (Staff/Sr. Staff) (Bengaluru)
🏢 MediaTek
📍 Bengaluru