SoC Coherency Verification Engineer | KWK992

SoC Coherency Verification Engineer | KWK992

21 Dec
|
Intel Technologies
|
Bengaluru

21 Dec

Intel Technologies

Bengaluru

Job Description



SoC Coherency Verification Engineer Job Description

The Xeon Server Solutions(XSS) Group is searching for an energetic passionate and process oriented Verification Engineers to work on multiple SOCs.Responsibilities include, but not limited to - -Should be able to develop Power Management Test plans and worked with the teams for implementation.-Should be well verged with Power Management verification concepts/methodologies with implementation.-Extensive working knowledge for SOC/SS low power mode techniques like Deep Sleep , isolation , power/voltage/clock gating , reset , retention and wake up techniques etc.

-Power Management feature/specification understanding by interacting with RTL designers/Architecture team and implementing end to end.-Should have NLP UPF/CPF low power simulations working knowledge , upf/cpf simulation debugging and building UPF testbench .-Need to develop the SV tests as required as per the Test plan.-Need to develop the assertions/checker as required.-Need to develop the complete coverage for a given feature and should be able to close it with sign-off metrics.Required Skills - -Strong SV/UVM fundamentals-Working knowledge of SOC Testbenches , testcases/checker/monitors implementation -Verdi/DVE waveform debugger working knowledge is required.-Assertions driven verification-Coverage driven verification-AXI/AHB/AMBA protocols-Power aware gate level verification is plus.-Good communication skills and experience working with folks in different functions and teams locally and in other countries



Qualifications



Should have Bachelors at least 7 years experience or Masters at least 5 years experience in Electrical/Electronics/Computer Engineering. Exposure to X86 or ARM architecture Strong understanding of multi-processor, multi-level cache, memory-ordering and coherent Mesh/Fabric concepts Previous experience in cache coherency protocols like ACE, CHI. Previous experience in using random stimulus for cache coherency verification at IP/sub-system/SoC to achieve desired Pre-Silicon coverage and recreate Post-Silicon scenarios.

The original job offer can be found in Kit Job:
https://www.kitjob.in/job/25758771/soc-coherency-verification-engineer-kwk992-bengaluru/?utm_source=html

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