ZZ-293 - DFT engineer

ZZ-293 - DFT engineer

21 Dec
|
Intel Technologies
|
Bengaluru

21 Dec

Intel Technologies

Bengaluru

Job Description



DFT engineer Job Description

Role and Responsibilities? DFT domain expertise on ATPG SCAN responsible for coverage improvement at_speed and stuck_at? Domain involves Analog IP as well as Test Chip SoC environment includes timing aware GLS closure and delivery of patterns to High Volume ATE team? Familiar with Mentor or Tetramax atpg tool is must for this role? Technically well verse with SCAN Architecture,

implementation in netlist (SCAN Insertion flows)? Work with internal teams like Arch/ Design/ STA convergence team to address issues on implementation/ SDC/SDF files? Work with Post Silicon team to enable atpg pattern delivery as well as debug? Plus for the job but not a must have - ICL/PDL based flow validation? Other extended DFT domain knowledge on MBIST BISR/BIRA/JTAG implementation/usage is an advantageGroup Profile: Ip Department within Intel India is owns on next gen Analog IP's and Test chips on various process nodes within Intel process and foundry process. Group mission is to make IP production ready to our SOC customers within Intel. Opportunities are available in DFT domain to own complete end to end solution while enabling scan atpg Arch, implementation of logic design on ultiscan controller, coverage improvement and enabling post silicon ATE team with patterns. Looking for DFT ATPG scan centric skillset



Qualifications



Qualification and Experience Level: MS/MTech and 7 to 10years of experience in Scan ATPG simulation/Debug and collateral delivery

The original job offer can be found in Kit Job:
https://www.kitjob.in/job/25758779/zz-293-dft-engineer-bengaluru/?utm_source=html

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