SOC Design Engineer Lead/ Manager - UWG-776

SOC Design Engineer Lead/ Manager - UWG-776

21 Dec
|
Intel Technologies
|
Bengaluru

21 Dec

Intel Technologies

Bengaluru

Job Description



SOC Design Engineer Lead/ Manager Job Description

Oversees definition design verification and documentation for SoC System on a Chip development Determines architecture design logic design and system simulation Defines module interfacesformats for simulation Performs Logic design for integration of cell libraries functional units and subsystems into SoC full chip designs Register Transfer Level coding and simulation for SoCs Contributes to the development of multidimensional designs involving the layout of complex integrated circuits Performs all aspects of the SoC design flow from highlevel design to synthesis place and route timing and power to create a design database that is ready for manufacturing Analyzes equipment to establish operation infrastructure conducts experimental tests and evaluates results May also review vendor capability to support development



Qualifications



Job Description The Core and Client Development Group is looking for a highly motivated SOC RTL Design Engineer Lead Manager to join the compute die frontend design team for the next generation of Client SOC In this role the candidates responsibilities include although not limited to Integration of complex IPs requires gaining high level of expertise in the IPs Define module interfacesformats for simulation Perform integration of cell libraries functional units and subsystems into SoC full chip designs RTL coding and simulation for SoCs Perform all aspects of the SoC design flow from highlevel design to synthesis timing and power to create a design database that is ready for manufacturing Design and integration methodology development and enforcement Run analyze and fix various quality check tools and flows such as CDC lint VCLP etc Define power domains using UPF and hit performance power and area targets Work with backend engineers on pre and post physical design timing closure Work with verification engineering to debug test cases in RTL and Gate Level simulation environment Work with crossfunctional teams to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process As a lead manager set priorities for the team get results across boundaries ensure an inclusive work environment develop employees Qualifications Bachelors in ElectricalComputer Engineering Computer Science or related field plus 10 years of relevant experience OR a Masters degree in ElectricalComputer Engineering Computer Science or related field with 8years of relevant experience Strong RTL design fundamentals

The original job offer can be found in Kit Job:
https://www.kitjob.in/job/25758782/soc-design-engineer-lead-manager-uwg-776-bengaluru/?utm_source=html

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