Why Ambit Are you up for a career that throws challenges and at the same time gives you a sense of pride in what you do Ambit offers it s people the ideal platform to toil and grow in the semiconductor design profession Our people have complete freedom to operate in their own adaptable ways and support that help them to learn and enhance their skills further Ambit firmly believes that for a company to grow big through innovation its people must be given a free hand to experiment and innovate The cheerful and bubbly work environment at Ambit portrays the commitment of the management for its people and their values Come join us today for a bright future in semiconductor design services Qualification Bachelor s or Master s degree in Electrical Electronics Engineering Computer Engineering or a related field Experience 5 - 8 Years Notice Period Immediate - 30 Days We are seeking a highly skilled and motivated Senior Formal Verification Engineer to lead formal verification efforts for complex digital designs The ideal candidate will have extensive hands-on experience using commercial formal verification tools especially JasperGold to ensure design correctness using mathematical methods and detect corner-case bugs early in the design cycle This role requires close collaboration with architecture design and simulation teams to define strategies and achieve verification closure Key Responsibilities Develop and implement comprehensive formal verification strategies and plans at the IP subsystem and SoC levels Create and maintain formal models and properties using SystemVerilog Assertions SVA or Property Specification Language PSL Apply advanced formal techniques including property checking sequential equivalence checking SEC and formal coverage analysis Analyze formal results identify unreachable code or vacuous properties and refine models and constraints to achieve coverage sign-off Collaborate closely with RTL designers to debug complex design issues provide root-cause analysis and suggest design improvements Build reusable and scalable formal verification environments and deploy relevant tools and methodologies across teams Evaluate and recommend EDA solutions for formal verification driving continuous improvement in methodologies and flows Mentor and provide guidance to junior engineers in formal verification techniques and tool usage Document verification plans test cases assumptions and final results for design sign-off Required Skills and Experience Education Bachelor s or Master s degree in Electrical Electronics Engineering Computer Engineering or a related field Experience Minimum of 5 years of experience in formal verification of complex digital designs Formal Tools Expertise Strong proficiency in commercial formal verification tools specifically Cadence JasperGold Experience with Synopsys VC-Formal or Mentor Questa Formal is a plus Languages Expertise in formal property languages SVA PSL and proficiency in HDLs such as SystemVerilog or Verilog Methodologies Strong understanding of formal verification methodologies abstraction techniques and convergence strategies Protocols Experience verifying designs involving industry-standard high-speed protocols like AXI AHB APB PCIe etc is highly desirable Scripting Proficiency in scripting languages e g Python Perl Tcl for automation and data analysis within Unix Linux environments Soft Skills Excellent problem-solving analytical and communication skills with the ability to work effectively in a cross-functional team environment