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Remote: Hybrid

RTL Design Engineer (SDC Constraints)Experience: 7+ YearsLocation: BangaloreWork Mode: Hybrid / RemoteJob OverviewWe are looking for a highly skilled Senior RTL ASIC Design Engineer with solid hands-on experience in SDC Constraints. The ideal candidate will have deep expertise in RTL design, timing constraints, and close collaboration with synthesis and STA teams.Key ResponsibilitiesDesign and develop RTL (Verilog/SystemVerilog) for complex ASIC blocks and subsystemsCreate, review, and maintain SDC constraints (clock definitions, I/O constraints, false paths, multicycle paths, exceptions, etc.)Work closely with synthesis, STA, physical design, and verification teams to achieve timing closurePerform RTL quality checks, linting,



and CDC analysisSupport timing debugging and constraint optimization across multiple design iterationsParticipate in architecture discussions and design reviewsEnsure deliverables meet performance, power, and area (PPA) goals.Mandatory Skills & Experience7+ years of hands-on experience in RTL ASIC designStrong and mandatory expertise in SDCClocking strategiesTiming exceptionsConstraint validation and debugProficiency in Verilog/SystemVerilogSolid understanding of ASIC design flow (RTL → Synthesis → STA → P&R;)Experience working with Synopsys tools (DC, PrimeTime – preferred)Robust knowledge of timing concepts and timing closureExcellent debugging and problem-solving skillsGood to HaveExperience in low-power design techniquesExposure to CDC/RDC methodologiesExperience with complex SoC designsScripting knowledge (Tcl / Perl / Python)Prior experience working with global or distributed teams

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📌 Rtl Asic Design Engineer Narela (India)
🏢 ACL Digital
📍 India