B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of solid, hands on block/sub HM level Timing closure or chip top level timing closure. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage

Skills Required

- Netlist and constraint sign in checks and validation.
- Prime time constraint development at full chip level and clean up.
- Multimode multi corner timing knowledge and timing closure at sub HM/block/top level.
- Top level timing closure with sign off STA in MMMC with Xtalk and OCV.
- Top level ECO implementation strategy development for netlist, RTL and timing level changes
- Scripting experience in Perl/TCL.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions .
- Technologies from 28nm and below.
- Technical leadership and ability to mentor and make the team deliver.

Location: Bangalore, Hyderabad, Chennai and Delhi

send your resumes to [email protected]

📌 STA Lead : Static Timing Analysis (Bengaluru)
🏢 The Nanopore Site
📍 Bengaluru