We are seeking an experienced, highly motivated and high-caliber individual with below expertise. Sr Staff RTL Design Engineer (R&D; engineering)

Experience: 9yrs to 15yrs

BSEE with 9 years of relevant experience OR MSEE with 8 years of relevant experience.

Expertise in RTL development using Verilog or System Verilog, with a robust background in digital design principles.

Hands-on experience with Xilinx and Altera FPGA platforms, including familiarity with Xilinx Vivado and related tools.

Proficiency in developing large, complex EDA software and managing the full design flow from concept to lab bring-up.

Advanced problem-solving and debugging skills, especially in digital verification, emulation, and prototyping environments.

Experience with scripting languages such as Tcl, Python, Perl, and a solid understanding of system and CPU architecture (DMA, interrupts, etc.).

Exposure to embedded system development and interface protocols (USB, PCIe, DDR, AXI).

Designing and developing advanced FPGA-based prototyping solutions,



integrating both hardware and software components.

Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.

Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.

Developing and maintaining complex EDA (Electronic Design Automation) software for high-performance prototyping systems.

Implementing digital debug, verification, emulation, and prototyping strategies to ensure robust and reliable designs.

Creating RTL for interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.

📌 Design Engineer (Bengaluru)
🏢 Synopsys
📍 Bengaluru