- We are seeking a talented Senior ASIC Verification Engineer to join our dynamic team.
- The successful candidate will be responsible for leading and executing verification efforts for complex ASIC designs, ensuring the quality and reliability of our products.
- Develop and maintain verification plans, testbenches, and test cases for ASIC designs.
- Collaborate with design and architecture teams to understand design specifications and requirements.
- Design and implement SystemVerilog/UVM-based verification environments.
- Create and execute test cases to verify functionality, performance, and compliance with specifications.
- Debug failures and drive issues to closure, working closely with cross-functional teams.
- Mentor junior team members and provide technical guidance.
- Contribute to the continuous improvement of verification methodologies and best practices.
- Create and maintain verification environments for SOCs.
- Drive verification to closure for IP, subsystem and SOC level.
- Implement functional coverage and code coverage for the modules and drive to closure along with designers
- Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.
- >8 years of experience in ASIC verification, preferably in a senior or lead role.
- Strong expertise in SystemVerilog, UVM, OOP concepts and verification methodologies.
- Experience with verification tools such as VCS, QuestaSim, or similar.
- Proven track record of successfully delivering complex ASIC verification projects.
- Excellent problem-solving and debugging skills.
- Solid communication and teamwork abilities.
Preferred Qualifications:
- Experience with scripting languages such as Python or Perl.
- Knowledge of industry standards and protocols (e.g., PCIe, DDR, USB, Ethernet).
- Knowledge on the on chip interconnects, memory and processor subsystems.
- Familiarity with formal verification techniques.