- Role & responsibilities
- 10-20 years of experience with Bachelors degree in Electronics Engineering from Malaysia.
- Experience in Physical Design with PNR flow from RTL to GDS flow,
- Knowledgeable in Static Timing Analysis, Power Analysis and Innovus.
- Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages.
- Experience in modifying STA constraints to check timing closure feasibility
- Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targets
- Experience in FinFET & Dual Patterning nodes such as 14/10/7/5/3/2nm
Please forward your updated profile to
[email protected]
📌 Physical Design Lead/Manager (Telangana)
🏢 Quest Global
📍 Telangana