- End-to-end RTL to GDS implementation of complex IPs and supporting the SOC customers
- Working with RTL team to resolve timing and congestion issues
- Build and develop methodology to converge multiple PNR blocks from RTL to GDS
- Analyze design metrics and make implementation choices to optimize PPA
PREFERRED EXPERIENCE:
- ASIC design flow and direct experience with ASIC design in sub-7nm technology nodes
- Circuit timing/STA, and practical experience with Prime Time or equivalent tools
- Low power digital design and analysis
- Expertise in synthesis and physical design flows
- Modern SOC tools including Synopsys Fusion compiler, Primetime and Redhawk
- TCL, Perl, Python scripting
- Solid verbal and written communication skills
- Ability to organize and present complex technical information
- Fluent in working with Linux environment
- Minimum 2 years of industry experience
Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 PD Engineer (Karnataka)
🏢 Proxelera
📍 Karnataka
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