At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design verification of ASICs for Palladium.

- Position is based in Bangalore
- Will have to work at IP, Sub-System and SOC level verification.
- Test plan creation, functional coverage plan and coding of functional coverage bins.
- Will be involved in post silicon validation/bring up.

Job Requirements:

- Robust expertise in Verilog, HVL( SV/Specman e) with UVM/OVM/eRM methodology.
- Experience in functional coverage/code coverage/assertions development and closure.
- Experience in test plan creation.
- Exposure to PCIe and LPDDR verification.
- Strong debug skills
- Should be process oriented and have a passion for scripting/automation.
- Should be a good team player
- Effective cross-team communication and documentation skill is strongly preferred.

Minimal qualification requires BS/MS degree ECE or CS with 4+ years of experience in related fields.

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📌 Lead Design Engineer (India)
🏢 Cadence Design Systems
📍 India