Principal Engineer, Systems Design Engineering (Bengaluru)

Principal Engineer, Systems Design Engineering (Bengaluru)

30 Jul
|
Sandisk
|
Bengaluru

30 Jul

Sandisk

Bengaluru

Company Description

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.
Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.
Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in effective operations. With our global reach,



we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Job Description

Role Summary
Own the end-to-end PCIe system design for an NVMe SSD product line across client laptops and enterprise servers, from PHY/MAC review through ASIC/SoC integration, PCIe SFR/register analysis, and firmware design guidelines for robust link training, link transitions, low-power behavior. This role sits at the intersection of PCIe spec compliance, NVMe behavior, FW architecture, platform interoperability, and power/performance tuning.
Key Responsibilities
- Own system‑level PCIe Gen5/Gen6 architecture from an NVMe SSD endpoint perspective
- Define and review PCIe + NVMe integration across SSD products
- PHY + MAC IP review, integration requirements and constraints
- SoC/ASIC integration: clocks, resets, power domains, straps, lane mapping, sidebands
- PCIe SFR + FW guidelines: flow control, LTSSM observability, power states, error handl

📌 Principal Engineer, Systems Design Engineering (Bengaluru)
🏢 Sandisk
📍 Bengaluru

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