? Hiring: Physical Design Engineer
? Location: Bengaluru
? Experience: 3–10 Years
⏳ Notice Period: Immediate to 30 Days Preferred

Job Responsibilities
Execute complete ASIC Physical Design flow from Netlist to GDSII.
Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Timing Closure.
Achieve PPA (Performance, Power, and Area) targets and improve QoR.
Perform Physical Verification (DRC, LVS, Antenna) and support sign-off activities.
Work on ECO implementation and timing closure using PrimeTime.
Collaborate with RTL, Synthesis, STA, DFT, and Sign-off teams.
Required Skills
Hands-on experience with Cadence Innovus and/or Synopsys ICC2/Fusion Compiler.
Robust knowledge of Floorplanning, Placement, CTS, Routing, STA, and Physical Verification.
Good understanding of MMMC, OCV/AOCV/POCV, SI/Crosstalk, and advanced technology nodes (16nm/7nm/5nm/3nm).
Experience with IR Drop, EM analysis, and Low Power design is an added advantage.
Strong TCL scripting, debugging, and problem-solving skills.
Excellent communication and teamwork skills.

Education
Bachelor's or Master's degree in Electronics, Electrical, VLSI, Microelectronics, or a related field.

📌 Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru