Location: Bay Area, US
Experience: 5+ Years
Employment Type: Full-Time
Key Responsibilities
Develop comprehensive verification plans and testbench architectures
Design and implement verification environments using System Verilog and UVM
Verify complex IPs and SoCs involving PCIe, CXL, UCIe, or similar high-speed protocols
Develop test cases, assertions, coverage models, and debug failing scenarios
Perform functional, protocol, and regression verification
Work closely with RTL designers, architects, and validation teams to ensure first-pass silicon success
Required Skil
5+ years of experience in Design Verification
Robust expertise in System Verilog, UVM, and scripting (Python/Perl/Shell
Hands-on experience with PCIe, CXL, UCIe, AXI, AHB, APB, or other industry-standard protocol
Experience in assertion-based verification (SVA) and functional coverage
Strong debugging skills and understanding of digital design fundamentals
Experience with industry-standard simulators such as VCS, Xcelium, or Quest