Key Responsibilities
- Lead the Memory Controller DV group and define verification strategy, architecture, and execution plans.
- Develop and enhance functional verification environments using SystemVerilog and UVM methodologies.
- Define and implement constrained-random verification, functional coverage, and formal property verification strategies.
- Create and review detailed verification test plans and ensure completeness of coverage for DDR/memory controller features.
- Ensure verification quality metrics and signoff requirements are met for all customer configurations.
- Work closely with RTL, subsystem, and performance teams to resolve design and verification issues.




- Drive development and adoption of advanced verification methodologies and best practices.
- Manage project execution, DV status tracking, and delivery timelines.
- Engage in customer-facing activities including pre-sales, post-sales support, and technical issue resolution.
- Collaborate with Marketing, Application Engineering (AE), and Release teams on product validation and delivery.
- Mentor and guide junior engineers to improve technical capability and productivity.
- Review and ensure robustness of verification environments and regression suites.

📌 Sr Principal Design Engineer (Noida)
🏢 Cadence
📍 Noida