Key Responsibilities
Customer Engagement & Support
- Serve as primary technical interface between customers, R&D;, and system validation teams.
- Provide pre-sales and post-sales support for memory IP integration and deployment.
- Respond to customer queries with accurate and timely technical solutions.

Memory IP Integration & Debug
- Support pre-silicon integration and implementation of memory subsystems (Controller + PHY).
- Assist customers in RTL and gate-level simulations for functional verification.
- Debug and resolve complex memory subsystem issues across design and integration stages.
- Support timing closure and physical implementation challenges.

System Validation & Review
- Participate in SOC integration, implementation, and design reviews for memory systems.
- Assist in post-silicon bring-up and production testing activities.




- Collaborate on system-level validation of DDR/LPDDR/HBM/GDDR interfaces.

Engineering & Analysis
- Work with static timing analysis, synthesis, and verification flows.
- Support DFT methodologies and test flow integration.
- Read schematics and participate in signal integrity (SI) and power integrity (PI) reviews.
- Engage in package and board-level design discussions.

Documentation & Process Improvement
- Contribute to development and refinement of technical documentation and customer checklists.
- Improve workflows for memory IP deployment and support processes.

AI & Analytics Enablement
- Leverage AI-based tools to improve productivity and decision-making.
- Use analytics tools to derive insights from complex design and validation data.

📌 Lead Product Engineer (Pune)
🏢 Cadence
📍 Pune