6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Positive knowledge of Power is preferable.
- Strong Domain Knowledge on RTL Design, implementation, and Timing analysis.
- Experience with RTL coding using Verilog/VHDL/System Verilog.
- Experience in micro-architecture & designing cores and ASICs.
- Familiar with the Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc.
- Exposure in scripting (Pearl/Python/TCL).
- Strong debugging capabilities at Synthesis, timing analysis & implementation
- Collaborate closely with cross-function team to research, design and implement performance, constraints and power management strategy for product roadmap.
- Good team player.
Need to interact with the other teams/verification engineers proactively.
- Ability to debug and solve issues independently.
About Company
ACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack — from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.
📌 Lead RTL Design Engineer (Chennai)
🏢 ACL Digital
📍 Chennai
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