Principal RTL Design Engineer - ASIC Design (Uttar Pradesh)

Principal RTL Design Engineer - ASIC Design (Uttar Pradesh)

30 Jul
|
Vitestork Consulting
|
Uttar Pradesh

30 Jul

Vitestork Consulting

Uttar Pradesh

1) Principal RTL Design Engineer - ASIC Design , ARM, SOC Architecture

Job Description

- Bachelors or Master s degree or equivalent experience in Electronics/Electrical Engineering with 14-18 years of RTL design experience.
- Hands on experience in RTL coding, debugging, verification, synthesis and timing closure.
- Strong experience in ARM based SOC architecture and ASIC design flow.
- AMBA protocols (AXI, AHB, APB), clock/reset domains and memory sub-systems.
- Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis.
- Familiarity with formal verification techniques, static/agile power checks.
- Proficiency in scripting and automation using Python.
- Excellent leadership, communication skills.




- Experience working with global cross-functional teams.
- Working knowledge of safety-critical design flows in automotive systems.
- Knowledge of Automotive Functional Safety ISO26262 is a plus.

Skills:

ASIC Design , Microarchitecture , ARM, SOC Architecture

Job Location:

Bengaluru , Noida

Experience:

14 -20 Yrs

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Principal RTL Design Engineer - ASIC Design (Uttar Pradesh)
🏢 Vitestork Consulting
📍 Uttar Pradesh

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