- Bachelors or Master s degree or equivalent experience in Electronics/Electrical Engineering with 14-18 years of RTL design experience.
- Hands on experience in RTL coding, debugging, verification, synthesis and timing closure.
- Strong experience in ARM based SOC architecture and ASIC design flow.
- AMBA protocols (AXI, AHB, APB), clock/reset domains and memory sub-systems.
- Experience with EDA tools for synthesis, LINT, CDC, RDC and timing analysis.
- Familiarity with formal verification techniques, static/agile power checks.
- Proficiency in scripting and automation using Python.
- Excellent leadership, communication skills.
- Experience working with global cross-functional teams.
- Working knowledge of safety-critical design flows in automotive systems.
- Knowledge of Automotive Functional Safety ISO26262 is a plus.
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