Description:

The Digital IP team within Analog Devices Inc. is responsible for developing, curating, and providing reusable strategic IPs to Business Units to accelerate product development across the company. The team is looking for an experienced Digital Design Staff Engineer / Lead who will be responsible for providing technical leadership to the digital design team, while managing IP development and delivery.

The ideal candidate would be someone with strong technical background combined with management acumen and demonstrable ability to handle ambiguity while still finding creative ways to make things happen.

A key focus area for this position includes interacting and engaging with internal customers to communicate, identify, improve, and maintain developed IP, as well as scout for 3rd party IPs and evaluate them on a regular basis for future requirements.

Job Responsibilities:

- Provide technical leadership and mentorship to digital design engineers across CDC, low power design, synthesis and timing closure, DFT improvements, and silicon debug
- Architect and design key digital blocks (accelerators, datapath IPs) in Verilog/SystemVerilog with configurability to optimize Power, Performance, and Area (PPA)
- Demonstrate deep understanding of heterogeneous processor subsystems (A55, M55, M4, U55, RISC V, DSP) and supporting infrastructure including caches, interconnects, GIC, DMA, MMU, CoreSight debug/trace, TZC, SMPU, and SPU
- Collaborate closely with product teams, program managers, and leadership to align schedules, milestones, commitments, and deliverables
- Drive adoption of AI tools (e.g., Copilot and approved third party tools) to improve efficiency and accelerate execution




- Build and lead expertise in complex interfaces and protocols including DDR, Ethernet, eMMC/SD, MIPI, DisplayPort, HDMI, PCIe, and high speed D2D
- Drive development of IP centric design management infrastructure and flows across Methodics, Perforce, GitHub, and IP catalog systems
- Develop and maintain a digital IP catalog to enable efficient information sharing and reuse across business units
- Package digital IPs for seamless integration across design stages, including RTL, constraints, CDC and timing waivers, DFT DRCs/waivers, and software programming sequences
- Conduct detailed design reviews and enforce adherence to quality metrics and best practices
- Lead evaluation of third party IPs on PPA, design quality, DFT robustness, DV maturity, and integration ease; provide clear recommendations
- Establish consistent benchmarking and evaluation flows for in house and third party IPs
- Manage and streamline consolidation and curation of digital IP assets, including standard peripherals, processor cores, and high speed interface IPs
- Reduce complexity and ambiguity across teams and processes by distilling technical detail into explicit, actionable guidance and recommendations

Position Requirements :

- Minimum B.E. /B. Tech degree in Electrical/Electronics/Computer science




- 12+ years of relevant experience with a strong focus on definition/ architecture/ u-arch/ design and hands-on RTL coding experience using Verilog and System-Verilog
- Strong understanding of all aspects of ASIC/SoC product development incl Design Verification/ timing constraints/ closure, physical implementation, quality assurance flows with hands-on prior experience in a few of these aspects
- Proven experience in managing/ handling large complex hardware projects in lead role
- Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions
- Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality
- Strong knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis, low power design
- Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis
- Ability to technically mentor a large digital design team
- Good interpersonal, teamwork and communication skills to drive discussions logically & effectively with teams spread geographically
- Strong understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols
- Knowledge of Processor/SoC architecture and/or DSP fundamentals
- Serve as the focal point for communications. Compile regular status updates for all stakeholders and effectively escalate critical issues and risks as necessary

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Staff Engineer, Digital Design Engineering (Karnataka)
🏢 Analog Devices
📍 Karnataka