We are hiring Senior Analog Layout Engineers with robust hands-on experience in Custom Analog/Mixed-Signal Layout for advanced TSMC technology nodes (7nm/5nm/3nm/2nm).
Required Skills
- Analog/Mixed-Signal Layout
- TSMC 7nm / 5nm / 3nm / 2nm
- Cadence Virtuoso
- FinFET technology
- Device Matching, Common Centroid, Shielding, Guard Rings
- DRC, LVS, ERC, PEX, EM/IR checks
- Experience with analog blocks such as PLL, ADC/DAC, LDO, Bandgap, SerDes, PMIC, Memory Interface
Qualification
- Bachelor's or Master's in ECE, EEE, VLSI, or Microelectronics.
Location: Bangalore
Notice Period: Immediate to 15 Days only