Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for cutting-edge solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.
Job Description
The position involves design verification of next generation IP’s /SoC’s with emphasis on verifying and signing off performance and power along with functionality by developing the needed RNM models . This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS .
Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification.
Responsibilities:
- To work in AMS Verification domain with relevant experience in mixed signal SOCs or subsystems/IPs.
- Leading a project for AMS requirements is a value add.
- Proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools
- Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus.
- Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS)
- Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus
- Functional knowledge of analog and mixed signal building blocks,