Job Description Hi All,
n Job Location: Bangalore
n Notice Period: 15 days to 30 Days
n Minimum: 5+ Years
n 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.
n 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.
n 3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.
n 4. Experience with hardware architecture exploration, performance modelling will be a big plus.
n 5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.
n 6.Must have experience in Lint and CDC.
n 7.Must have RTL Design worked on PCIe/CXL
n Thanks,
n K Himabindu