Job Description Job Title: Technical Lead - Central Design Methodology (CDM) Team
n Location: Bangalore
n Exp: 15+ yrs
n We are seeking an experienced and highly motivated Technical Lead to spearhead the Central Design Methodology (CDM) Team to drive the development, deployment, and continuous improvement of R&D; organization's design (EDA/CAD) methodologies and processes for IP and SoC development across Analog/Mixed-Signal (AMS), Digital, and RF design domains. This role is pivotal in defining, developing, and deploying cutting-edge tools, flows, recipes, methodologies, design-processes, gate-checklist that improve PPA, design efficiency and productivity, quality, reuse, robustness and time-to-market across multiple product lines.
n This role requires deep technical expertise in semiconductor Chip design methodologies, strong leadership skills, and the ability to collaborate effectively with R&D; design functions/components (AMS, Digital, RF, PD, DV, DFT, Emulation/Validation) and EDA vendors.
n Key Responsibilities
n Methodology & Process Leadership and Strategy
n n Define and execute the roadmap for design (EDA/CAD) tools, flows, recipes, methodologies, design-processes covering Analog, Mixed-Signal, Digital, and RF IP and SoC development.
n Collaborate with R&D; design functions/components (AMS, Digital, RF, PD, DV, DFT, Emulation/Validation) to align methodologies with organizational goals.
n Establish standardized baseline for design, verification, implementation, signoff, release processes and quality gate-checklist across R&D; design functions/components. And drive continuous improvement from that.
n Drive methodology adoption and ensure alignment with organizational quality, reliability, productivity and schedule goals.
n Lead the evaluation, bring-in and deployment of next-generation design technologies and current capabilities, automation solutions, and AI-assisted engineering workflows.
n n Design Flow, Methodology and Process Development
n n Architect, implement and maintain standardized and scalable end-to-end Chip design flows for:
n Analog and Mixed-Signal design




n Digital front-end and back-end design and implementation
n RF design and integration
n DFT design and integration
n IP development, reuse and manage
n Full-chip SoC integration
n Verification, Emulation/Validation
n Develop process for quality gate-checklist, signoff and design release (cross-functional design hands-off).
n Evaluate and integrate EDA tools, automation frameworks, scripting solutions.
n Establish flow interoperability across multiple EDA platforms and foundry technologies.
n Establish best practices for design reuse, verification, release and signoff.
n n Automation and Infrastructure
n n Lead the development of automation frameworks, scripts, and infrastructure to improve engineering efficiency.
n Drive implementation of reusable design kits, PDK integration methodologies, verification environments, and regression systems.
n Develop dashboards, metrics, and analytics to measure design quality, productivity, and methodology compliance.
n n Cross-Functional Collaboration
n n Partner and closely work with R&D; Design Functions/Components (AMS, Digital, RF, PD, DFT, DV, Emulation/Validation) to develop their TFM, Recipe and Design-process and PPA push.
n Work closely with EDA vendors and foundry partners to influence tool capabilities and resolve methodology challenges.
n Support project teams during methodology & process deployment, training, and issue resolution.
n Ensure seamless integration of analog, mixed-signal and digital IPs into complex SoCs.
n n Innovation & Continuous Improvement
n n Stay ahead of industry trends in semiconductor design methodologies.
n Drive adoption of advanced techniques such as machine learning–based design optimization, cloud-enabled design environments,



and AI-assisted verification.
n Champion efficiency improvements in design cycle time, PPA and quality metrics.
n n Key Success Metrics
n n Improved PPA of the Chips (IP/SoC).
n Improved design productivity and reduced development cycle time.
n Increased IP reuse and methodology adoption across projects.
n Enhanced first-pass silicon success rate.
n Reduction in design and verification turnaround time.
n Improved design quality and signoff robustness.
n Successful deployment of automation and methodology innovations.
n Team growth, engagement, and technical excellence.
n n Required Qualifications
n Technical Skills
n n Strong understanding of:
n Analog and Mixed-Signal design, verification and signoff tool, flow, methodologies (TFM) and design-process
n Digital design, verification and signoff TFM and design-process
n RF design, verification and signoff TFM and design-process
n Design-for-Test (DFT) TFM
n IP qualification, reuse, release and management frameworks
n Hands-on expertise in EDA tools (Cadence, Synopsys, Mentor, etc.) and scripting (Python, TCL, Perl).
n Proven track record in IP and SoC development methodologies and processes from concept to silicon.
n Experience with documentation & issue tracking process (Confluence/JIRA), revision control systems (LSF), workflow automation, and large-scale compute (HPC) environments.
n n Education & Experience
n n Master's or Ph.D. in Electrical Engineering, Electronics, Computer Engineering or related field.
n 15+ years of experience in semiconductor design methodologies & processes with exposure to AMS, Digital, and RF domains.
n 5+ years of experience leading methodology, EDA, CAD, design enablement, or related technical teams.
n Excellent leadership, communication, and collaboration skills.
n n Preferred Qualifications
n n Experience in developing Central CAD Methodologies for large design organizations.
n Knowledge of advanced process nodes (FinFET, RF CMOS, SiC, GAN/GAS, etc.).
n Familiarity with AI/ML applications in EDA.
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📌 Technical Lead-Central Design Methodology (CDM) Team (Bengaluru)
🏢 L&T Semiconductor Technologies
📍 Bengaluru