Job Description ASIC RTL Design Engineer
n Location: Bengaluru, India
n Experience: 5–10 Years
n Role Summary
n We are looking for a highly skilled ASIC RTL Design Engineer to design and develop high-performance PCI Express (PCIe) IPs and SoC components. The ideal candidate will have strong expertise in microarchitecture definition, RTL design, and implementation of high-speed digital logic for next-generation semiconductor products.
n Key Responsibilities
n n Design and implement RTL for PCI Express (PCIe) controllers, subsystems, and high-speed digital IPs.
n Translate architecture specifications into efficient microarchitecture and high-quality RTL.
n Develop scalable, high-performance, and low-power digital designs using Verilog/SystemVerilog.
n Perform functional analysis, logic optimization, lint, CDC, and synthesis-ready RTL development.
n Collaborate with Architecture, Verification, Physical Design, DFT, and Firmware teams throughout the development cycle.
n Support design reviews, debug functional issues, and resolve silicon bring-up challenges.
n Drive design quality through coding guidelines, documentation, and best engineering practices.
n n Required Skills




n n 5–10 years of hands-on experience in ASIC RTL Design.
n Strong expertise in Microarchitecture, RTL design, and digital logic implementation.
n Solid experience with PCI Express (PCIe Gen4/Gen5/Gen6) architecture and protocol.
n Proficiency in Verilog/SystemVerilog with a strong understanding of synchronous digital design.
n Experience with Lint, CDC, RDC, Synthesis, and timing-aware RTL development.
n Good understanding of AMBA protocols (AXI/AHB/APB) and SoC integration.
n Familiarity with scripting using Python, Perl, Tcl, or Shell.
n Experience with Synopsys or Cadence RTL development and synthesis tools.
n Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
n n Preferred Qualifications
n n Experience designing high-performance CPU, AI/ML, Networking, Storage, or Datacenter SoCs.
n Exposure to CXL, NVMe, DDR, or Ethernet protocols is an added advantage.
n Robust debugging, analytical, and problem-solving skills with the ability to work in cross-functional engineering teams.
n

📌 ASIC RTL Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru