Key Responsibilities
RTL Design & Development
- Design and develop high-quality RTL using Verilog for complex digital systems
- Implement and optimize micro-architecture for performance and functional correctness
- Ensure adherence to design specifications and industry standards

Verification & Debugging
- Develop and debug testbenches using SystemVerilog and UVM methodology
- Analyze functional issues and resolve complex verification failures
- Ensure full coverage of design scenarios including corner cases and protocol compliance

Protocol Expertise
- Work extensively on PCIe-based design and verification flows (mandatory)
- Support or design for advanced protocols such as CXL / PXC (preferred)




- Ensure compliance with protocol specifications and timing requirements

Collaboration & Integration
- Work closely with design, verification, and validation teams
- Participate in design reviews and cross-functional technical discussions
- Contribute to integration of RTL blocks into larger system architectures

Quality & Optimization
- Ensure high-quality RTL through linting, simulation, and verification flows
- Optimize designs for performance, area, and power where applicable
- Support regression testing and continuous integration flows

📌 Sr Principal Design Engineer (Bengaluru)
🏢 Cadence
📍 Bengaluru