The DFX DV Lead will be responsible for driving Design-for-Test Verification (DFX DV) activities for SoC/IP programs as part of the dedicated ODC team. The role requires robust ownership of verification planning, testbench development, regression execution, debug, and coverage closure activities across multiple DFT features and flows.

The candidate is expected to work closely with DFT, DV, ATPG, Integration, and Design teams to ensure high-quality milestone-driven execution.

Key Responsibilities
Drive DFX DV execution across SoC/IP programs
Develop and maintain DFX verification environments and testbenches
Develop directed/random testcases for DFT features
Execute regressions and analyze failures
Perform debug using waveforms, logs, and simulation results
Support coverage closure and verification signoff activities
Collaborate with ATPG, MBIST, Integration, and Timing teams
Support GLS, emulation, and pattern validation activities
Participate in technical reviews and milestone tracking




Ensure deliverables meet client quality and schedule expectations
Drive issue closure proactively with strong ownership mindset

Mandatory Technical Skills
Solid experience in:
SystemVerilog
UVM
Verilog
DFT Verification
Scan Verification
ATPG Verification
JTAG / Boundary Scan verification
Strong debugging skills using
Waveform viewers
Log analysis
Simulation debug methodologies
Experience with
Directed and random verification methodologies
Regression management
Coverage analysis and closure
Solid scripting skills
Perl
Python
Shell scripting

Preferred Skills
Prior AMD project experience
Experience with
Tessent flows
GLS
Emulation environments
Pattern validation
Knowledge of
AMBA protocols
IEEE 1149.1 / IEEE 1687
Security DFT concepts
Advanced node exposure
5nm
4nm
3nmRole & responsibilities

Preferred candidate profile

📌 Dfx Dv Lead Bengaluru
🏢 G.t.d Technologies
📍 Bengaluru