Role Overview and Responsibilities
Test Plan Creation: Build detailed verification plans from architectural specifications.
Testbench Development: Build reusable test settings using SystemVerilog and Universal Verification Methodology (UVM).
Test Execution & Debugging: Run constrained-random and directed tests, find root causes of bugs, and fix RTL failures with design teams.
Coverage Closure: Track code and functional coverage to ensure complete design validation.
Required Skills and Qualifications
Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Electronics.
Languages: Robust proficiency in SystemVerilog, UVM, and scripting languages like Python or Perl.
Protocols: Knowledge of industry standards such as AMBA AXI/APB, PCIe, or USB.
Tools: Experience with EDA simulators like Synopsys VCS, Cadence Xcelium, or Mentor Questa.