We are looking for an experienced Lead Physical Design Engineer who is passionate about delivering high-quality ASIC/SoC designs and enjoys taking ownership from floorplanning to tape-out. In this role, you’ll lead the complete physical design implementation, working closely with RTL, STA, DFT, and other cross-functional teams to achieve the best PPA while meeting aggressive project timelines. You should be comfortable handling complex blocks independently, driving timing closure, resolving congestion, power, IR/EM, and signal integrity challenges, and ensuring signoff quality.

Beyond technical expertise, we’re looking for someone who enjoys mentoring engineers, influencing design methodologies, and fostering a collaborative team workplace. A strong understanding of advanced technology nodes, hands-on experience with industry-standard EDA tools such as ICC2, Innovus, PrimeTime, Fusion Compiler, or Tempus, along with scripting skills in TCL, Python, or Perl, are essential. The ideal candidate is a proactive problem solver with strong technical leadership, excellent communication skills,



and a track record of delivering successful tape-outs while driving quality, innovation, and execution excellence.

Qualification & skills:
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related field.
7 years of hands-on experience in ASIC/SoC Physical Design.
Proven experience leading block-level or full-chip physical design projects through successful tape-outs.

⁠ Strong hands-on experience across the complete Physical Design flow from floorplanning to signoff.
Expertise in timing closure, PPA optimization, and physical verification.
Experience with advanced technology nodes and industry-standard Physical Design tools.
Proficiency in TCL, Python, or Shell scripting.
Robust problem-solving, collaboration, and mentoring skills with the ability to drive projects independently.

Pay: ₹25,000,000.00 - ₹35,000,000.00 per year

Perks
Flexible schedule
Paid time off
Work from home

Work Location: In person

📌 Lead Physical Design Engineer Hsr Layout
🏢 THINSIL
📍 HSR Layout