The focus of this role is to plan, implement, and execute the physical design and verification of processing subsystems IP, resulting in meeting the signoff criteria for tapeout.
THE PERSON:
You have a passion for up-to-date, complex processor architecture, digital design, and Implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have solid analytical and problem-solving skills and are willing to learn and ready to take on problems.
PREFERRED EXPERIENCE:
12+ Years of experience in relevant domain.
Experienced with Blocklevel and toplevel physical implementation.
Positive understanding and hands-on experience in lower node technologies. (5nm or below)
Preferably working on low power or processor designs.
Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.
Scripting language experience: TCL, Python preferred.
Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in computer engineering/Electrical Engineering
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