As part of the SoC Design team, the engineer has technical responsibility for SoC design and integration efforts involving both AMD and third-party IPs. The role works closely with IP development, verification, front-end integration, and physical design teams throughout the SoC development cycle.
Key Responsibilities
SoC-level design and integration.
Integration of IPs, SoC fabric, voltage crossings, clock crossings, resets, fuses, and I/O.
RTL design and coding for SoC logic and features.
SoC power design and power implementation activities.
Static verification including:
RTL Lint
CDC (Clock Domain Crossing)
RDC (Reset Domain Crossing)
Power checks
Connectivity checks
Debugging simulation and integration issues spanning multiple IPs in collaboration with verification teams.
Supporting top-level synthesis and collaborating with physical design teams for full-chip implementation. Leading one of the design domains (integration, power, CDC/RDC, connectivity, etc.).
Required Skills
Verilog RTL development in CPU, SoC, or ASIC settings.
Solid understanding of:
SoC integration
SoC architecture
System interconnect protocols such as AXI and PCIe
Experience with:
UPF and low-power methodologies
Static timing analysis (STA)
Physical design interaction and implementation requirements
Familiarity with scripting languages such as Tcl, Perl, Ruby, or Shell.
Knowledge of formal verification techniques and tools.
Personal Attributes
Self-driven and able to work independently.
Strong written and verbal communication skills.
Solid problem-solving capability.
Experience Education
8+ years of SoC Design and Verilog RTL development experience.
BE/B.Tech/ME/M.Tech (ECE/EEE or equivalent).
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