1) Memory Layout Engineer - Junior/ senior lead/Architect - [ID 018]
B.Tech/M.Tech in Electrical Engineering, VLSI, or Microelectronics.
Experience: Typically ranges from 2 to 10+ years depending on whether the role is entry/mid-level or a senior lead/architect position.
Tools Software: Proficiency in standard EDA tools, primarily Virtuoso Layout Editor and Custom Compiler. Familiarity with verification tools like Mentor Calibre is often a strict requirement.
Scripting Languages: Solid capability in writing or modifying layout automation scripts (Python, Tcl, SKILL).
Knowledge Domain: Deep understanding of semiconductor physics, sub-micron/FinFET effects, pitch-matching, shielding, and parasitic capacitance mitigation.
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