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We are looking for a skilled Physical Design Engineer with hands-on experience in Full-Chip Floorplanning for complex ASIC/SoC designs. The ideal candidate should have strong expertise in die size estimation, macro and IO planning, power planning, congestion analysis, and floorplan optimization, with a solid understanding of the complete physical design flow through tape-out.

Key Requirements:
510 years of experience in Physical Design with robust Full-Chip Floorplanning expertise.
Hands-on experience in die size estimation, macro placement, IO planning, power grid design, and congestion optimization.
Valuable understanding of placement, CTS, routing, timing closure, and physical signoff.
Experience with advanced technology nodes (16nm/7nm/5nm preferred).
Proficiency with Cadence Innovus and/or Synopsys ICC2/Fusion Compiler.
Knowledge of IR drop, EM, SI, MMMC, and low-power implementation (UPF/CPF) is preferred.
Experience with at least one full-chip tape-out and robust Tcl scripting skills is an advantage.
Excellent analytical, debugging, and cross-functional collaboration skills.

📌 Physical Design Engineer Full Chip Floor Planning Fcfp Bengaluru
🏢 Proxelera
📍 Bengaluru