Role Description Required Skills 5+ years of experience in Memory Layout or Custom Layout Design. Hands-on experience with SRAM, ROM, CAM, Register Files, or Memory Compiler layouts. Robust expertise in Cadence Virtuoso. Valuable knowledge of Calibre DRC, LVS, ERC, and DFM.
Experience with advanced technology nodes (28nm, 16nm, 7nm, 5nm, or below). Understanding of layout effects, EM/IR, latch-up, antenna, and reliability concepts. Scripting knowledge in SKILL, Perl, Tcl, or Python is an added advantage. Excellent debugging, analytical, and problem-solving skills.
Preferred Qualifications Skills Analog Layout, LVS, SRAM, Python
📌 Technical Lead I Vlsi Ml Bd Bengaluru
🏢 UST
📍 Bengaluru
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