30 Jul
|
Texas Instruments
|
Bengaluru
30 Jul
Texas Instruments
Bengaluru
We are at a pivotal moment where technology is rapidly evolving, and we have some exciting prospects within our MCU organization that place us right at the center of this transformation.
Our current work is focused on developing solutions for high-growth markets such as AI-driven data centers and emerging domains like humanoid systems. These areas are shaping the future of computing, automation, and intelligent systems, and offer a unique chance to work on cutting-edge technologies with real-world impact.
If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, I encourage you to come forward and apply. This is an prospect to be part of a journey that is not only technically rewarding but also strategically significant.
Looking forward to seeing many of you take this step.
Role Title: SoC Chip Lead / design manager
Role Summary: Own end-to-end delivery of the first T28 industrial ASIC for the ASM Industrial business. This role combines full chip ownership with functional team leadership, ensuring first-time-right silicon, scalable architecture, and a strong RTL organization for future platforms.
Key Responsibilities:
Own SoC execution from spec → architecture → RTL → Silicon → mass production
Act as single technical owner (Chip Lead) for the first T28 industrial ASIC
Drive PPA, quality, cost, and schedule trade-offs
Lead execution across RTL, DV, DFT, PD and Validation.
Interface with Architecture, IP, FW/SW, Product, Business teams, PE team.
Own pre-silicon sign-off and post-silicon bring-up & validation
Lead and grow the design team
Ensure high-quality micro-architecture, coding, reuse, and integration
Balance hands-on technical leadership with people management
Minimum Qualifications:
Bachelors/Masters in EE or equivalent
12 years experience in complex SoC/ASIC development
Leadership experience in multiple SoC domains.
Robust expertise in: ARM-based systems, interconnects, Low-power design, clock/reset/power architecture
End-to-end SoC lifecycle exposure including RTL → PnR → timing closure
Solid pre- and post-silicon debug skills, Multiple successful tape-outs
Excellent communication and cross-team leadership skills
Preferred:
Prior Chip Lead / SoC Lead role
Experience with first-silicon or new-node (T28) programs
Industrial SoC exposure
Post-silicon bring-up and yield learning experience
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