Chennai, Tamil Nadu
Job Summary

Candidates with 1 to 3 years' experience is mandatory

Valuable understanding of ASIC/SoC life cycle

Experience writing ASIC/SoC testplans

Experience in writing verification strategy document

Key Responsibilities

UVM based testbench development:
Experience in ASIC/SoC Testbench definition

Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM)."

C based TB development:
Experience in developing TB components for SOC with C, SV

SV functional coverage, Assertions coding :
1.Expertise & hands-on experience in OVM/UVM methodologies using SV

2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.

Test case development, coding, execution, bug analysis :
Experience in developing TB components, including functional coverage implementation and assertion coding
Experience Set up functional coverage, write system assertions (SVA),



and analyze code coverage metrics to identify untested gaps in the design logic.

3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
Experince in SOC C based tests coding & debugging"

Skill Requirements

Gate Level Simulation:
Experience in Gate level simulation & netlist debugging

Regressions, coverage analysis

Exeprince in regression failure analayiss

Functioncal and Code Coverage closure

Other Requirements

Core Technical Skills

Languages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM.

Digital Logic: Solid foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
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📌 Designer Chennai
🏢 HCLTech
📍 Chennai