We are looking for experienced Static Timing Analysis (STA) Engineers to join a high-performance ASIC/SoC design team. The ideal candidate will have strong expertise in timing signoff, timing closure, and physical design, with hands-on experience in advanced technology nodes.

Key Responsibilities:

Perform block-level and full-chip Static Timing Analysis (STA) and timing signoff.

Drive timing closure across multiple process, voltage, and temperature (PVT) corners and operating modes (MMMC/MCMM).

Analyze and resolve setup/hold violations, crosstalk, and signal integrity issues.

Collaborate with Physical Design, RTL, CTS, and ECO teams to achieve timing closure.

Develop, validate, and maintain SDC timing constraints.

Perform timing ECO analysis and verification.

Automate STA flows using TCL, Perl, or Python scripting.

Debug complex timing issues and recommend optimization strategies.





Required Skills:

Solid hands-on experience with Synopsys PrimeTime and/or Cadence Tempus.

Expertise in STA, Timing Closure, MMMC/MCMM, OCV/AOCV/POCV, Signal Integrity, and Crosstalk.

Positive understanding of Physical Design flow, CTS, Place & Route (PnR), and ECO implementation.

Experience with advanced technology nodes (16nm/7nm/5nm/3nm preferred).

Proficiency in TCL scripting; Perl or Python is an added advantage.

Solid analytical, debugging, and communication skills.

Qualifications:

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.

4–12 years of experience in ASIC/SoC Physical Design or Static Timing Analysis.

📌 Senior Sta Engineer Tamil Nadu (India)
🏢 Mobiveil Technologies (India)
📍 India