Job Description Location: Hyderabad, India Experience: 7 25 years Key Responsibilities Verification Architecture Planning
Define and execute verification strategy for subsystems:
SPI, UART, I2C
Audio interfaces (I2S, TDM)
Power management digital controllers
Develop test plans with full functional and corner-case coverage
Identify verification risks and coverage gaps early

UVM-Based Verification Development
Build and maintain UVM/System Verilog testbenches
Develop:
Reusable VIPs and monitors
Scoreboards and checkers
Constrained-random stimulus
Implement protocol-aware verification components

Coverage Quality
Drive:
Functional coverage
Code coverage (line, toggle, FSM)
Ensure closure of:
Coverage goals
Assertion checks
Track and report verification metrics

Debug Validation
Debug RTL issues and root-cause failures
Work closely with RTL engineers on bug fixes and improvements
Support post-silicon validation with test reuse where applicable

System-Level Verification
Contribute to SoC-level verification:




Subsystem integration scenarios
Firmware-driven tests
Validate interactions across clock, reset, and power domains

Required Qualifications
7 25 years of DV experience in SoC/subsystem verification
Robust expertise in:
System Verilog and UVM
Functional coverage and assertions (SVA)
Experience verifying:
AMBA protocols (AXI/AHB/APB)
Peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications
Experience with mixed-signal verification settings (AMS co-sim is a plus)
Exposure to low-power verification (UPF/CPF)
Familiarity with ARM Cortex-M33 or RISC-V SoCs

Qualification:
Bachelors or Masters degree in Electronics/Electrical Engineering or related field

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Design Verification Professional Telangana (India)
🏢 Uandwe Technologies
📍 India