Key Responsibilities
- Develop and execute functional verification plans for complex digital and SoC-level designs
- Work with HDLs such as Verilog and/or VHDL for simulation and emulation tasks
- Build and maintain verification environments using SystemVerilog and UVM
- Debug design and verification issues using EDA tools (Cadence and other industry tools)
- Design and implement scalable and reusable verification testbenches and frameworks
- Perform simulation, regression testing, and coverage analysis for digital systems
- Develop automation scripts to improve verification efficiency and workflow
- Collaborate with design and architecture teams to ensure specification compliance
- Work on protocol-level verification for interfaces such as PCIe, USB 3/4, and DisplayPort (DP) where applicable
📌 Principal Product Validation Engineer (Noida)
🏢 Cadence
📍 Noida
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