Job DescriptionJob Title: Technical Lead - Central Design Methodology (CDM) Team NLocation: Bangalore NExp: 15+ yrs NWe are seeking an experienced and highly motivated Technical Lead to spearhead the Central Design Methodology (CDM) Team to drive the development, deployment, and continuous improvement of R&D; organization's design (EDA/CAD) methodologies and processes for IP and SoC development across Analog/Mixed-Signal (AMS), Digital, and RF design domains. This role is pivotal in defining, developing, and deploying cutting-edge tools, flows, recipes, methodologies, design-processes, gate-checklist that improve PPA, design efficiency and productivity, quality, reuse, robustness and time-to-market across multiple product lines. NThis role requires deep technical expertise in semiconductor Chip design methodologies, solid leadership skills, and the ability to collaborate effectively with R&D; design functions/components (AMS, Digital, RF, PD, DV, DFT, Emulation/Validation) and EDA vendors. NKey ResponsibilitiesnMethodology & Process Leadership and Strategy Nn Define and execute the roadmap for design (EDA/CAD) tools, flows, recipes, methodologies, design-processes covering Analog, Mixed-Signal, Digital, and RF IP and SoC development. N Collaborate with R&D; design functions/components (AMS, Digital, RF, PD, DV, DFT, Emulation/Validation) to align methodologies with organizational goals. N Establish standardized baseline for design, verification, implementation, signoff, release processes and quality gate-checklist across R&D; design functions/components. And drive continuous improvement from that. N Drive methodology adoption and ensure alignment with organizational quality, reliability, productivity and schedule goals. N Lead the evaluation, bring-in and deployment of next-generation design technologies and new capabilities, automation solutions, and AI-assisted engineering workflows. NnDesign Flow, Methodology and Process Development Nn Architect, implement and maintain standardized and scalable end-to-end Chip design flows for:



N Analog and Mixed-Signaldesign N Digital front-end and back-end design and implementation N RF design and integration N DFT design and integration N IP development, reuse and manage N Full-chip SoC integration N Verification, Emulation/Validation N Develop process for quality gate-checklist, signoff and design release (cross-functional design hands-off). N Evaluate and integrate EDA tools, automation frameworks, scripting solutions. N Establish flow interoperability across multiple EDA platforms and foundry technologies. N Establish best practices for design reuse, verification, release and signoff. NnAutomation and Infrastructure Nn Lead the development of automation frameworks, scripts, and infrastructure to improve engineering efficiency. N Drive implementation ofreusable design kits, PDK integration methodologies, verification environments, and regression systems. N Develop dashboards, metrics, and analytics to measure design quality, productivity, and methodology compliance. NnCross-Functional Collaboration Nn Partner and closely work with R&D; Design Functions/Components (AMS, Digital, RF, PD, DFT, DV, Emulation/Validation) to develop their TFM, Recipe and Design-process and PPA push. N Work closely with EDA vendors and foundry partners to influence tool capabilities and resolve methodology challenges. N Support project teams during methodology & process deployment, training, and issue resolution. N Ensure seamless integration of analog, mixed-signal and digital IPs into complex SoCs. NnInnovation & Continuous Improvement Nn Stay ahead of industry trends in semiconductor design methodologies. N Drive adoption of advanced techniques such as machine learning–based design optimization,



cloud-enabled design environments, and AI-assisted verification. N Champion efficiency improvements in design cycle time, PPA and quality metrics. NnKey Success Metrics Nn Improved PPA of the Chips (IP/SoC). N Improved design productivity and reduced development cycle time. N Increased IP reuse and methodology adoption across projects. N Enhanced first-pass silicon success rate. N Reduction in design andverification turnaround time. N Improved design qualityand signoff robustness. N Successful deployment of automation and methodology innovations. N Team growth, engagement, and technical excellence. NnRequired Qualifications NTechnical Skillsn N Strong understanding of: N Analog and Mixed-Signaldesign, verification and signoff tool, flow, methodologies (TFM) and design-process N Digital design, verification and signoff TFM and design-process N RF design, verificationand signoff TFM and design-process N Design-for-Test (DFT) TFM N IP qualification, reuse, release and management frameworks N Hands-on expertise in EDA tools (Cadence, Synopsys, Mentor, etc.) and scripting (Python, TCL, Perl). N Proven track record in IP and SoC development methodologies and processes from concept to silicon. N Experience with documentation & issue tracking process (Confluence/JIRA), revision control systems (LSF), workflow automation, and large-scale compute (HPC) environments. NnEducation & Experience Nn Master's or Ph.D.in Electrical Engineering, Electronics, Computer Engineering or related field. N 15+ years of experiencein semiconductor design methodologies & processes with exposure to AMS, Digital, and RF domains. N 5+ years of experience leading methodology, EDA, CAD, design enablement, or related technical teams. N Excellent leadership, communication, and collaboration skills. NnPreferred Qualifications Nn Experience in developing Central CAD Methodologies for large design organizations. N Knowledge of advanced process nodes (FinFET, RF CMOS, SiC, GAN/GAS, etc.). N Familiarity with AI/ML applications in EDA. N

📌 Technical Lead-Central Design Methodology (Cdm) Team (Karnataka)
🏢 L&T Semiconductor Technologies
📍 Karnataka